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ADM1041
Bit No.
Name
R/W
Description
0 1 2%
1 0 3%
1 1 4%
3–2
ssrs1, ssrs0
R/W
Soft-Start Step
b3 b2 Rise Time
0 0 300 μs
0 1 10 ms
1 0 20 ms
1 1 40 ms
1
0
add1
trim_lock
R/W
R/W
EEPROM programmable second address bit.
When this bit is set, the trim registers including this register are not writable via SMBus. To
make registers writable again, the trim-lock bit in the EEPROM must first be erased and the
value downloaded using either power-up or test download.
Table 26. Register 11h, Config5. Power-O n Default from EEPROM Register 8111h 8110h during Power-Up.
Bit No.
7
6
5
4–3
2
Name
curr_lim_dis
polpen0
polcbd0
Reserved
ocpts2
R/W
R/W
R/W
R/W
X
R/W
Description
Mask effect of OCP to general logic (status flag still gets asserted) when curr_lim_dis = 1.
Sets polarity of PEN output. Refer to the Configuration table (Table 45).
Don’t Care.
Set this bit to 1 when 0 OCP ridethrough is required. A small delay still exists. Refer to Reg 12h
1
0
gndok_dis
cbdlm
R/W
R/W
Disable gndok input to power management debounce logic.
Select CBD latch mode. 0 = nonlatching; 1 = latching.
Table 27. Register 12h, Config6. Power-On Default from EEPROM Register 8112h 8110h during Power-Up.
Bit No.
7
Name
rsm
R/W
R/W
Description
Restart Mode. When rsm = 1, the circuit attempts to restart the supply after an undervoltage or
overcurrent at about 1 second intervals.
Latch Mode. When rsm = 0, UV and OC faults latch the output off. Cycling PSON or removing the
supply to the IC is then required to reset the latch and permit a restart.
6
up_AC_OK_m
R/W
Configure microprocessor to control/gate signal from acinok to acsok.
0 = standalone.
1 = microprocessor support mode.
5
m_acsns_w
(W)
Microcessor control of acsok (AC SENSE ).
4–3
ocpts1, ocpts0
R/W
OCP Ridethrough (Reg 11h[2] = 0)
OCP Ridethrough (Reg11h[2] = 1)
b4 b3 Period b4 b3 Period
0 0 1 second 0 0 128 μs
0 1 2 seconds 0 1 256 μs
1 0 3 seconds 1 0 384 μs
1 1 4 seconds 1 1 512 μs
2
acss
(W)
AC Sense Mode. 0 means AC_OK is derived from AC SENSE 1, whereas 1 means AC_OK is derived from
AC SENSE 2.
1
0
m_pson_w
I SHARE _clamp
(W)
R/W
Microprocessor control of pson.
0 = 75%. Set current share clamp release threshold.
1 = 88%.
Table 28. Register 13h, Config7. Power-On Default from EEPROM Register 8113h during Power-Up.
Bit No.
Name
R/W
Description
Rev. A | Page 47 of 64
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